Digital-to-analog converters (DAC's) are widely used in data transmission systems to convert input data bits into an analog waveform for transmission over a communications channel. In high- bit rate full-duplex telecommunication systems, high-precision DAC's are generally required to achieve satisfactory performance, e.g., for echo cancellation.
"2B1Q" refers to a telecommunications format which has been adopted as a standard in basic rate Integrated Services Digital Network (ISDN) systems (e.g. See, ANSI specification T1.601-1988) operating at 80 kbaud and in high-bit rate Digital Subscriber Line (HDSL) systems operating at 392 kbaud. In accordance with the 2B1Q format, two data bits are encoded into one level of a four level (quaternary) output pulse (hence, "2B1Q").
In order to achieve satisfactory performance in such systems, it is imperative that the four levels of the output pulse bear precise amplitude ratios relative to one another; e.g., +3, +1, -1, -3.
The present invention is directed to digital-to-analog converters for responding to multibit data input words to produce analog output waveforms comprised of multiple levels having precisely related amplitudes.
Pulse width modulation techniques have been used in the prior art to implement digital to analog conversion, primarily for low precision audio applications. For example, U.S. Pat. No. 3,506,848 describes a circuit which integrates a pulse at a fixed rate over an interval proportional to the desired analog output level. The pulse train is then filtered to provide the final analog output. U.S. Pat. No. 4,233,591 describes a technique whereby a single integration interval is divided into multiple elementary periods. The time constant of the integrator is then sped up to enhance the response speed of the analog output. U.S. Pat. No. 4,532,496 proposes another improvement in digital waveform generation, interspersing digital "staircase" outputs to a smoothing circuit.